1. Field of the Invention
The present invention relates to an intermediate potential generation circuit, and more particularly, to an intermediate potential generation circuit used for a semiconductor storage device.
2. Description of the Related Art
A dynamic random access memory (DRAM), which is one of semiconductor storage devices, includes a precharge circuit that precharges a bit line pair to an intermediate potential (½)Vcc of a power supply potential Vcc. The precharge circuit functions to precharge a sense amplifier of a cross couple type which is connected to amplify a minute voltage difference in the bit line pair, to the intermediate potential (½)Vcc. In recent years, with a demand to miniaturize diverse electronic devices and reduce electric power thereof, there is required a technology of accurately obtaining the intermediate potential (½)Vcc even if the power supply potential Vcc is low.
JP 08-171432 A discloses a related art pertaining to an intermediate potential generation circuit. FIG. 3 illustrates a configuration of the intermediate potential generation circuit disclosed in JP 08-171432 A. The intermediate potential generation circuit includes a reference potential generation section 1010 that generates two reference potentials Vref1 and Vref2, an output section 1012 that generates the intermediate potential (½)Vcc between the power supply potential Vcc and a ground potential Vss in response to those reference potentials Vref1 and Vref2, and an output node 1014.
The reference potential generation section 1010 includes a p-channel MOS transistor 1101, an n-channel MOS transistor 1102, a p-channel MOS transistor 1103, and an n-channel MOS transistor 1104. Those transistors 1101 to 1104 are connected in series between a power supply node 1100 to which the power supply potential Vcc is applied and a ground node 1200 to which the ground potential Vss is applied.
The p-channel MOS transistor 1101 has a source electrode connected to the power supply node 1100, and a gate electrode connected to the output node 1014. A back gate electrode of the p-channel MOS transistor 1101 is connected commonly to the source electrode. The n-channel MOS transistor 1102 has a drain electrode and a gate electrode connected to a drain electrode of the p-channel MOS transistor 1101. The drain electrode and the gate electrode of the n-channel MOS transistor 1102 are connected to each other. That is, the n-channel MOS transistor 1102 is diode-connected. The p-channel MOS transistor 1103 has a source electrode connected to a source electrode of the n-channel MOS transistor 1102, and a drain electrode and a gate electrode which are connected to each other. That is, the p-channel MOS transistor 1103 is diode-connected. A back gate electrode of the p-channel MOS transistor 1103 is connected commonly to the source electrode thereof. The n-channel MOS transistor 1104 has a drain electrode connected to the source electrode and the gate electrode of the p-channel MOS transistor 1103, a source electrode connected to the ground node 1200, and a gate electrode connected to the output node 1014. A substrate potential VBB lower than the ground potential Vss is applied to the back gate electrodes of the n-channel MOS transistors 1102 and 1104. The structure of the p-channel MOS transistor 1101 is the same as that of the p-channel MOS transistor 1103. Further, the structure of the n-channel MOS transistor 1102 is the same as that of the n-channel MOS transistor 1104.
The output section 1012 includes an n-channel MOS transistor 1121 and a p-channel MOS transistor 1122. Those transistors 1121 and 1122 are connected in series between the power supply node 1100 and the ground node 1200.
The n-channel MOS transistor 1121 has a drain electrode connected to the power supply node 1100, a source electrode connected to the output node 1014, and a gate electrode connected to the drain electrode and the gate electrode of the n-channel MOS transistor 1102. A threshold voltage of the n-channel MOS transistor 1121 is set to be substantially equal to or higher than a threshold voltage Vtn of the n-channel MOS transistor 1102.
The p-channel MOS transistor 1122 has a source electrode connected to the output node 1014, a drain electrode connected to the ground node 1200, and a gate electrode connected to the drain electrode and the gate electrode of the p-channel MOS transistor 1103. A threshold voltage of the p-channel MOS transistor 1122 is set to be equal to or higher than an absolute value |Vtp| of a threshold voltage of the p-channel MOS transistor 1103.
Now, an operation of the intermediate potential generation circuit is described. In the reference potential generation section 1010, the four transistors 1101 to 1104 are symmetrically arranged with respect to the node N3. With this arrangement, the potential (½)Vcc that is just a midpoint between the power supply potential Vcc and the ground potential Vss is generated at the node N3. Further, because the n-channel MOS transistor 1102 is diode-connected, a potential higher than that at the node N3 by the threshold voltage Vtn thereof, that is, a potential (½)Vcc+Vtn higher than the intermediate potential by the threshold voltage thereof is generated at the node N1 as a reference potential Vref1.
Further, because the p-channel MOS transistor 1103 is diode-connected as well, a potential lower than that at the node N3 by the absolute value |Vtp| of the threshold voltage thereof, that is, a potential (½)Vcc−|Vtp| lower than the intermediate potential by the absolute value of the threshold voltage thereof is generated at the node N2 as a reference potential Vref2.
The reference potential Vref1 generated in the reference potential generation section 1010 is applied to the gate electrode of the n-channel MOS transistor 1121 in the output section 1012. Further, the reference potential Vref2 is applied to the gate electrode of the p-channel MOS transistor 1122. Because the threshold voltage of the n-channel MOS transistor 1121 is set to be equal to or slightly higher than the threshold voltage of the n-channel MOS transistor 1102, the n-channel MOS transistor 1121 is slightly turned on.
Further, because an absolute value of the threshold voltage of the p-channel MOS transistor 1122 is set to be equal to or slightly higher than the absolute value |Vtp| of the threshold voltage of the p-channel MOS transistor 1103, the p-channel MOS transistor 1122 is also slightly turned on. Similarly, in the output section 1012, the transistors 1121 and 1122 are symmetrically arranged, and hence the intermediate potential (½)VCC is generated at the output node 1014.
A description is given of a case where a potential (hereinafter referred to as “output potential”) Vout of the output node 1014 is to be deviated from the intermediate potential (½)Vcc in the intermediate potential generation circuit. When the output potential Vout decreases, the gate potential to the source potential of the n-channel MOS transistor 1121 increases. As a result, the n-channel MOS transistor 1121 becomes smaller in conduction resistance, and a current flows from the power supply node 1100 to the output node 1014 through the transistor 1121. For that reason, the output potential Vout increases. Moreover, at this time, because the output potential Vout is applied to the gate electrode of the p-channel MOS transistor 1101, the conduction resistance of the transistor 1101 becomes smaller, and a current flows from the power supply node 1100 to the node N1 through the transistor 1101. Accordingly, when the output potential Vout decreases, the gate potential of the n-channel MOS transistor 1121 rapidly increases. As a result, the output potential Vout rapidly returns to the original intermediate potential (½)Vcc.
On the other hand, when the output potential Vout increases, the gate potential to the source potential of the p-channel MOS transistor 1122 becomes smaller, and hence the conduction resistance of the transistor 1122 becomes smaller. Accordingly, the output potential Vout decreases. Moreover, at this time, because the output potential Vout is applied to the gate electrode of the n-channel MOS transistor 1104, the conduction resistance of the transistor 1104 becomes smaller, and the potential at the node N2 rapidly decreases. Accordingly, the output potential Vout rapidly returns to the original when increasing from the intermediate potential (½)Vcc.
In the intermediate potential generation circuit disclosed in JP 08-171432 A, because the four transistors 1101 to 1104 are connected in series between the power supply potential Vcc and the ground potential Vss of the reference potential generation section 1010, the minimum operating voltage of 4*Vt (Vt is the threshold voltage) or higher is required. The threshold voltage Vth between the gate and the source of the MOS transistor, that is, a minimum voltage required for allowing a current to flow between the source and the drain of the MOS transistor is normally about 0.5 V, and therefore the minimum operating voltage in the reference potential generation section 1010 is 4*Vt 2 V or more.
As described above, with power saving of the system device such as a cellular phone, the demand to decrease the voltage in a semiconductor integrated device has been increased. In a DRAM, which is a semiconductor storage device essential in configuring the system, in particular, a DRAM mixedly mounted on an application specific integrated circuit (ASIC), it is required to suppress the power supply potential to about 1 V or lower. For that reason, the above-mentioned configuration that requires the power supply potential of 2 V or higher cannot meet that demand.
Further, in the intermediate potential generation circuit of the above related art, the gate voltages of source followers in the output section 1012 are applied from the reference voltage generation section 1010, separately. Therefore, the respective source followers are structurally turned on, and the through current cannot be prevented from occurring. This is another factor to hinder the voltage from being decreased.